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? e92928f0z-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. absolute maximum ratings (ta=25 ?) supply voltage av dd , dv dd 7v input voltage (all pins) v in v dd +0.5 to v ss ?.5 v output current (for each channel) i out 0 to 15 ma storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , av ss 4.75 to 5.25 v dv dd , dv ss 4.75 to 5.25 v reference input voltage v ref 1.8 to 2.0 v clock pulse width t pw1, t pw0 9 ns (min.) to 1.1 s (max.) operating temperature topr ?0 to +85 ? description the CXD2307R is a 10-bit high-speed d/a converter for video band, featuring rgb 3-channel i/o. this is ideal for use in high-definition tvs and high-resolution displays. features resolution 10-bit maximum conversion speed 50msps rgb 3-channel i/o differential linearity error 0.5lsb low power consumption; 300 mw (max.) single +5 v power supply low glitch stand-by function structure silicon gate cmos ic 10-bit 50msps rgb 3-channel d/a converter 64 pin lqfp (plastic) CXD2307R
? CXD2307R block diagram 4lsb's current cells 6msb's current cells clock generator current cells (for full scale) 4lsb's current cells 6msb's current cells clock generator current cells (for full scale) 4lsb's current cells 6msb's current cells clock generator current cells (for full scale) bias voltage generator decoder latches decoder decoder latches decoder decoder latches decoder 40 39 38 37 36 35 34 33 41 42 43 45 46 47 48 49 52 53 54 55 56 57 58 59 63 64 60 61 62 32 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 2 3 4 5 6 7 8 1 44 50 51 31 (lsb) r0 r1 r2 r3 r4 r5 r6 r7 r8 (msb) r9 (lsb) g0 g1 g2 g3 g4 g5 g6 g7 g8 (msb) g9 (lsb) b0 b1 b2 b3 b4 b5 b6 b7 b8 (msb) b9 blk ce dv dd av dd av dd vgr ro ro rck ror vrr irr av dd av dd vgg go go gck rog vrg irg av dd av dd vgb bo bo bck rob vrb irb vb av ss av ss dv ss
3 CXD2307R pin configuration 52 53 54 55 56 57 58 59 60 63 64 61 62 49 50 51 20 21 22 23 24 25 26 27 28 29 30 31 32 17 18 19 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 avss ro ro av dd av dd go go av dd av dd bo bo av dd av dd dv dd (lsb) r0 r1 gck rck ce blk b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (lsb) g9 g8 vgb rob vgg rog vgr ror vrb vrg vrr irb irg irr avss vb dvss bck r2 r3 r4 r5 r6 r7 r8 r9 (lsb) g0 g1 g2 g3 g4 g5 g6 g7 pin description and equivalent circuit 63 to 8 9 to 18 19 to 28 29 30 31 32 33 34 r0 to r9 g0 to g9 b0 to b9 blk ce rck gck bck dv ss i pin no. symbol i/o equivalent circuit description dv dd dv ss to 33 63 digital input. r0 (lsb) to r9 (msb) g0 (lsb) to g9 (msb) b0 (lsb) to b9 (msb) blanking input. this is synchronized with the clock input signal for each channel. no signal for high (0 v output). output generated for low. chip enable pin. this is not synchronized with the clock input signal. no signal at for high (0 v output) to minimize power consumption. clock input. digital ground.
4 CXD2307R 35 36, 49 43 45 47 44 46 48 37 38 39 40 41 42 vb av ss ror rog rob vgr vgg vgb irr irg irb vrr vrg vrb o o i o i pin no. symbol i/o equivalent circuit description dv dd dv ss dv dd 35 av ss av ss av dd av dd av ss av dd av ss av dd 45 47 43 46 48 44 39 37 38 42 41 40 connect to dv ss with a capacitor of approximately 0.1 f. analog grounds. connect to vgr, vgg, and vgb with the control method of output amplitude. see application circuit. connect a capacitor of approximately 0.1 f. connect to av ss with a resistance of 3.3 k ? . set output full-scale value (2.0 v).
5 CXD2307R 50 54 58 51 55 59 52, 53, 56, 57, 60, 61 62 ro go bo ro go bo av dd dv dd o pin no. symbol i/o equivalent circuit description av dd av ss av dd av ss 50 54 58 51 55 59 current output pins. output can be retrieved by connecting a resistance of 200 ? to av ss . reverse current output pins. normally connected to av ss . analog v dd . digital v dd . aa aa aaa aaa aa aa aaa aaa t pw1 t pw0 t s t h t s t h t s t h t pd t pd t pd clk data d/a out 1.5v 100% 50% 0% i/o correspondence table (output full-scale voltage: 2.00 v) input code output voltage msb lsb 1 1 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 0 : 0 0 0 0 0 0 0 0 0 0 2.0 v 1.0 v 0 v timing chart
6 CXD2307R electrical characteristics (f clk =50 mhz, av dd =dv dd =5 v, r out =200 ? , v ref =2.0 v, ta=25 c) item resolution conversion speed integral non-linearity error differential non-linearity error precision guaranteed output voltage range output full-scale voltage output full-scale ratio ? 1 output full-scale current output offset voltage glitch energy crosstalk supply current analog input resistance input capacitance output capacitance digital input voltage digital input current setup time hold time propagation delay time ce enable time ? 2 ce disable time ? 2 symbol n f clk e l e d v oc v fs f sr i fs v os ge ct i dd i stb r in c i c o v ih v il i ih i il ts th t pd t e t d measurement conditions av dd =dv dd =4.75 to 5.25 v ta= 20 to 85 c endpoint for the same gain (see the application circuit) when 0000000000 data input when 10 mhz sine wave date input ce= l ce= h vgr, vgg, vgb, vrr, vrg, vrb ro,go,bo av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c av dd =dv dd =4.75 to 5.25 v ta= 20 to +75 c ce=h l ce=l h min. 0.5 2.0 0.5 1.8 1.8 0 1 2.15 5 7 3 typ. 10 1.9 1.9 1.5 9.5 100 54 55 50 10 1 1 max. 50 2.0 0.5 2.0 2.0 3.0 10 1 60 1 9 0.85 5 2 2 unit bit msps lsb lsb v v % ma mv pv s db ma m ? pf pf v a ns ns ns ms ms full-scale voltage for each channel ? 1 full-scale output ratio = full-scale voltage average value for each channel 1 100 (%) ? 2 when the external capacitors for the vg pins are 0.1 f. electrical characteristics measurement circuit analog input resistance measurement circuit digital input current CXD2307R +5.25v av dd , dv dd av ss , dv ss v a }
7 CXD2307R vgr to vgb 44, 46, 48 ror to rob 43, 45, 47 vrr to vrb 40 to 42 irr to irb 37 to 39 rck 10 bit counter with latch clk 50mh z square wave gck bck 0.1 dvss 200 avss 200 avss 200 avss 3.3k 2v 0.1 av dd oscillo scope blk ce vb ro ro go bo bo r0 to r9 63 to 8 g0 to g9 9 to 18 b0 to b9 19 to 28 35 33 31 32 go 29 30 delay controller delay controller 50 51 54 55 58 59 maximum conversion speed measurement circuit vgr to vgb 44, 46, 48 vrr to vrb 40 to 42 irr to irb 37 to 39 rck 10 bit counter with latch clk 50mh z square wave gck bck 0.1 dvss 200 avss 200 avss 200 avss 3.3k 2v 0.1 av dd oscillo scope blk ce vb ro ro go bo bo r0 to r9 63 to 8 g0 to g9 9 to 18 b0 to b9 19 to 28 35 33 31 32 go 29 30 50 51 54 55 58 59 ror to rob 43, 45, 47 setup time hold time measurement circuit glitch energy } cross talk measurement circuit clk 50mh z square wave digital waveform generator all 1 vgr to vgb 44, 46, 48 ror to rob 43, 45, 47 vrr to vrb 40 to 42 irr to irb 37 to 39 rck gck bck 0.1 dvss 200 avss 200 avss 200 avss 3.3k 2v 0.1 av dd blk ce vb ro ro go bo bo r0 to r9 63 to 8 g0 to g9 9 to 18 b0 to b9 19 to 28 35 33 31 32 go 29 30 50 51 54 55 58 59 spectrum analyzer
8 CXD2307R vgr to vgb 44, 46, 48 ror to rob 43, 45, 47 vrr to vrb 40 to 42 irr to irb 37 to 39 rck clk 50mh z square wave gck bck 0.1 dvss 200 avss 200 avss 200 avss 3.3k 2v 0.1 av dd oscillo scope blk ce vb ro ro go bo bo r0 to r9 63 to 8 g0 to g9 9 to 18 b0 to b9 19 to 28 35 33 31 32 go 29 30 50 51 54 55 58 59 frequency demultiplier dc characteristics measurement circuit vgr to vgb 44, 46, 48 vrr to vrb 40 to 42 irr to irb 37 to 39 rck clk 50mh z square wave gck bck 0.1 dvss 200 avss 200 avss 200 avss 3.3k 2v 0.1 av dd blk ce vb ro ro go bo bo r0 to r9 63 to 8 g0 to g9 9 to 18 b0 to b9 19 to 28 35 33 31 32 go 29 30 50 51 54 55 58 59 ror to rob 43, 45, 47 controller dvm propagation delay time measurement circuit
9 CXD2307R application circuit (gain equal) 0.1f 3.3k ? nc nc 1k ? nc nc 0.1f dv dd dv ss av dd av ss 200 ? rout 200 ? gout 200 ? bout 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 52 53 54 55 56 57 58 59 60 63 64 61 62 49 50 51 20 21 22 23 24 25 26 27 28 29 30 31 32 17 18 19 g channel input r channel input 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 clock input b channel input 0.1f 3.3k ? 1k ? 0.1f dv dd dv ss av dd av ss 200 ? rout 200 ? gout 200 ? bout 40 39 38 37 36 35 34 33 41 42 43 44 45 46 47 48 52 53 54 55 56 57 58 59 60 63 64 61 62 49 50 51 20 21 22 23 24 25 26 27 28 29 30 31 32 17 18 19 g channel input r channel input 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 clock input b channel input (gain independently) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
10 CXD2307R notes on operation how to select the output resistance the CXD2307R is a d/a converter of the current output type. to obtain the output voltage connect the resistance to the current output pins ro, go and bo. for specifications we have: output full scale voltage v fs =1.8 to 2.0 [v] output full scale current i fs =less than 15 [ma] calculate the output resistance value from the relation of v fs =i fs r out . also, 16 times resistance of the output resistance is connected to reference current pin irr, irg and irb. in some cases, however, this turns out to be a value that does not actually exist. in such a case a value close to it can be used as a substitute. here please note that v fs becomes v fs =v ref 16r out /r ir . v ref is the voltage set at v rr ,v rg and the vrb pin, and r out is the resistance connected to the current output pins ro, go and bo while r ir is connected to irr, irg and irb. increasing the resistance value can curb power consumption. on the other hand glitch energy and data settling time will inversely increase. set the most suitable value according to the desired application. phase relation between data and clock to obtain the expected performance as a d/a converter, it is necessary to set properly the phase relation between data and clock applied from the exterior. be sure to satisfy the provisions of the setup time (t s ) and hold time (t h ) as stipulated in the electrical characteristics. power supply and ground to reduce noise effects separate analog and digital systems in the device periphery. for power supply pins, both digital and analog, bypass respective grounds by using a ceramic capacitor of about 0.1 f, as close as possible to the pin. latch up analog power supply and digital power supply have to be common at the pcb power supply source. this is to prevent latch up due to voltage difference between av dd and dv dd pins when power supply is turned on. ro, go and bo pins the ro, go and bo pins are the inverted current output pins described in the pin description. the sums shown below become the constant value for any input data. a) the sum of the currents output from ro and ro b) the sum of the currents output from go and go c) the sum of the currents output from bo and bo however, the performances such as the linearity error of the inverted current output pin output current is not guaranteed. output full-scale voltage for the applications using the rgb signal, the color balance may be broken up when the no-adjusted output full-scale voltage is used.
11 CXD2307R c av ss dv ss av ss dv ss av dd dv dd CXD2307R c dv dd digital ic +5v latch up prevention the CXD2307R is a cmos ic which requires latch up precautions. latch up is mainly generated by the lag in the voltage rising time of av dd and dv dd , when power supply is on. 1. correct usage a. when analog and digital supplies are from different sources b. when analog and digital supplies are from a common source (i) (ii) av dd +5v av ss dv ss av ss dv ss av dd dv dd CXD2307R c dv dd digital ic c +5v av ss dv ss av ss dv ss av dd dv dd CXD2307R c dv dd digital ic c +5v
12 CXD2307R 2. example when latch up easily occurs a. when analog and digital supplies are from different sources b. when analog and digital supplies are from common source (i) (ii) av dd +5v av ss dv ss av ss dv ss av dd dv dd CXD2307R dv dd digital ic c +5v c c av ss dv ss av ss dv ss av dd dv dd CXD2307R dv dd digital ic av dd c +5v +5v av ss dv ss av ss dv ss av dd dv dd CXD2307R dv dd digital ic av dd c
13 CXD2307R example of representative characteristics output frequency vs. crosstalk output frequency f o [h z ] 100k 1m 10m crosstalk ct [db] 80 70 60 50 40 av dd =dv dd =5v f clk =50msps r out =200 ? r ir =3.3k ? ta=25 c ambient temperature vs. current consumption ambient temperature ta [ c] current consumption i dd [ma] 60 50 20 0 25 50 75 ambient temperature vs. full-scale voltage full-scale voltage v fs [v] 1.9 1.8 200 255075 ambient temperature ta [ c] av dd =dv dd =5v f clk =50msps v ref =2.0v r out =200 r ir =3.3k av dd =dv dd =5v f clk =50msps v ref =2.0v r out =200 r ir =3.3k ? ? ? ?
sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin 42/copper alloy package structure 12.0 0.2 ? 10.0 0.1 (0.22) b 1 16 17 32 33 48 49 64 0.1 0.1 0.5 0.2 0? to 10? 64pin lqfp (plastic) lqfp-64p-l01 p-lqfp64-10x10-0.5 0.3g detail a 0.5 0.2 (11.0) a 1.5 ?0.1 + 0.2 0.1 solder plating note: dimension ? does not include mold protrusion. 0.13 m 0.5 b = 0.18 ?0.03 ( 0.18 ) (0.127) + 0.08 0.127 ?0.02 + 0.05 detail b : solder package outline unit : mm CXD2307R 14
15 CXD2307R sony corporation sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin copper alloy package structure 12.0 0.2 ? 10.0 0.1 (0.22) b 1 16 17 32 33 48 49 64 0.1 0.1 0.5 0.2 0 ? to 10 ? 64pin lqfp (plastic) lqfp-64p-l01 p-lqfp64-10x10-0.5 0.3g detail a 0.5 0.2 (11.0) a 1.5 0.1 + 0.2 0.1 palladium plating note: dimension ? does not include mold protrusion. 0.13 m 0.5 b = 0.18 0.03 0.125 0.04 detail b : palladium package outline unit : mm

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